Standing for Reduced Instruction Set Computer according to ABBREVIATIONFINDER.ORG, RISC is a particularly fast type of processor that uses highly developed pipeline technology, which enables it to operate with a high level of simultaneity. These types of processors are the opposite of the so-called CISC, much more common.
The beginnings of RISC technology emerged in the academic environment, in 1980, at the University of Berkeley California, where Dr. David A. Patterson started a project called RISC I, obtaining results in just 19 months, followed by RISC II, SOAR Smalltalk on a RISC and SPUR (Symbolic Processing on a RISC), but simultaneously, at Stanford University, Dr. John Hennesy also started a RISC implementation project, called MIPS, followed by the MIPS-XMP system, focused on the symbolic process, thus demonstrating the speed capabilities of the RISC architecture.
Both professors were quickly involved in commercial product projects, and specifically, the one named Hennesy was one of the founders of MIPS Computer Systems, while Patterson acted as a consultant during the development of the first SPARC.
RISC processors use only simple instructions that can be executed quickly. For this reason, they are usually architectures based on general-purpose registers that always operate on operands that are stored in the processor, near the execution unit.
In this way, the MULT command could be divided into three separate commands: LOAD, which moves data from the memory bank to a register; PROD, which finds the product of two operands located in the registers; and STORE, which moves data from a register to the memory bank.
To perform the series of steps outlined in the CISC philosophy, a programmer should code the instruction in 4 lines of assembly code:
- LOAD A, (2: 3)
- LOAD B, (5: 2)
- PROD A, B
- STORE (2: 3), A
The design time of these products is significantly reduced, which reduces their final cost, and therefore, their expectations are increased, by being able to reach the market in a more adequate time, and with fewer possibilities of errors, they are more efficient, of Smaller dimensions and lower power, the most successful multiprocessor RISC workstations, are based on different versions of SPARC technology : superSPARC and HyperSPARC.
- The characteristics common to all RISC processors, source of their high performance capabilities, are: Load / Store instruction set model which means: Load-Store. Only Load / Store instructions access memory; all other operations in a RISC take place on its large set of registers. This simplifies addressing and shortens CPU cycle times, also facilitates the management of page faults in virtual memory environments, allows a high level of concurrency as a result of the independence of Load / Store operations execution of the rest of the instructions.
- Non-destructive three-way architecture. The CISC processors destroy the information that exists in any of the registers, as a consequence of the normal execution of instructions; This is due to its two-way architecture, so the result of an operation overwrites one of the registers that contained the operands. In contrast, RISC instructions, with three addresses, contain the fields of the two operands and their result. Therefore, both the source and destination operands are kept in the registers after the operation has been completed. This non-destructive architecture allows compilers to organize the instructions in such a way as to keep the pipelines of the chip full, and therefore to reuse the operands optimizing the concurrency.
- Simple, fixed-format instructions with few addressing modes. Simple instructions significantly reduce the effort to decode them, and make them easier to run in pipelines. Fixed-length instructions, with fixed formats, imply that opcodes and operand opcode fields are always encoded in the same positions, allowing access to registers at the same time that the opcode is being decoded. All instructions have a length equivalent to one word and are aligned in memory in word boundaries word boundaries, since they cannot be divided into pieces that can be on different pages.
- Lack of microcode. Microcode does not lend itself to execution in single cycles, since it requires that the hardware be dedicated to its dynamic interpretation. Microcode programming does not make software faster than programming with a simple set of instructions. All functions and control in RISC processors are hardwired for maximum speed and efficiency.
- Execution in pipelined ducts. Simple, fixed-format, single-cycle instructions allow the different stages of the execution cycles, search or fetch, decode, execute, and write the result or result write-back for multiple instructions, to be performed simultaneously, in a more efficient way. simple and effective.
- Execution in single single-cycle cycles. The direct result of the instruction sets offered by RISC processors is that each instruction can be executed in a single CPU cycle. This invalidates the belief that microcode microinstructions, created to be executed in a single processor cycle, are faster than assembly language instructions. Since the cache is built on the same technology as the microprogram control storage, a single instruction can be executed at the same speed as a microinstruction. Running in single cycles also simplifies the management of interrupts and pipelines.
It works very differently from the CISC, its objective is not to save external efforts by the software with its access to RAM, but to facilitate that the instructions are executed as quickly as possible. The way to achieve this is by simplifying the type of instructions that the processor executes. Thus, the shorter and simpler instructions on a RISC processor are capable of executing much faster than the longer and more complex instructions on a CISC chip. However, this design requires much more RAM and more advanced compiler technology.
The relative simplicity of the architecture of RISC processors leads to shorter design cycles when new versions are developed, making it always possible to apply the latest semiconductor technologies. As a result, not only do RISC processors tend to offer 2-4 times more system throughput, but the capacity jumps that occur from generation to generation are much greater than CISCs.
The commands embedded in the RISC chip in its ROM consist of several small instructions that perform a single task. The applications are here in charge of telling the processor what combination of these instructions it must execute to complete a larger operation.
The RISC commands are all the same size and are loaded and stored in the same way. As these instructions are small and simple, they do not need to be decoded into smaller instructions as in the case of CISC chips, since they already constitute decoded units themselves. This is why the RISC processor does not spend time verifying the size of the command, decoding it, or figuring out how to load and save it.
The RISC processor can also execute up to 10 commands at the same time since the software compiler is the one that determines which commands are independent and therefore it is possible to execute several at the same time.
As the RISC commands are simpler, the circuitry they go through is also simpler. These commands go through fewer transistors, so they run faster. To execute a single instruction, one clock cycle usually suffices.
- The RISC strategy also has great advantages. Because each instruction performs a very simple operation, the code will execute in approximately the same time as the MULT command of the CISC architecture. These reduced RISC instructions require less hardware and are simpler than complex instructions, leaving more room for general purpose registers. Also, optimizations on simpler hardware are much easier to perform.
- RISC has reached all semiconductor manufacturers: AMD, Intel, MIPS, Motorola, ROSS, and all of them are products used by manufacturers of computers and workstations: Apple, DEC, HP, IBM, SUN, among others and their corresponding clones.
- The CPU works faster by using fewer clock cycles to execute instructions.
- It uses a non-destructive address system in RAM. This means that unlike CISC, RISC preserves the two operands and their result after performing its operations in memory, reducing the execution of new operations. Each instruction can be executed in a single CPU cycle.
The definition of RISC is the future of computing. Within the next five years, a completely new Computing Standard will emerge based on RISC architectures. RISC computers will completely redefine the price-performance curve that currently exists in the computer industry based on CISC computers, and will become the standard of the computer industry that will take us to the 19th century.